A dual damascene integration scheme is a process integration scheme employed in semiconductor manufacturing to form metal vias and metal lines with a single metal fill process and a single metal planarization process. Two lithographic masks are employed to pattern via holes and metal line cavities separately in a conventional dual damascene integration scheme. Variations in the conventional dual damascene integration scheme includes a via first dual damascene integration scheme, in which via cavities are formed prior to patterning of line cavities, and a line first dual damascene integration scheme, in which line cavities are formed prior to patterning of via cavities. The via cavities and the line cavities formed in a dielectric layer are filled by the metal fill process at the same time. Upon planarization of the metal layer, metal vias filling the via cavities and metal lines filling the line cavities are simultaneously formed.
Since the line cavities and the via cavities are formed in separate lithographic processes, it is necessary to control the overlay between the pattern for the via cavities and the pattern for the line cavities. For high performance semiconductor chips employing high density semiconductor devices and high density metal wiring, critical masks, i.e., lithographic masks having the smallest possible overlay tolerance in alignment with another level during the lithographic imaging process, need to be employed for patterning the via cavities and the line cavities to insure that sufficient overlap is present between the resulting metal vias and metal lines. Use of such critical masks increases manufacturing cost significantly since lithographic processing steps, and especially critical level lithographic processing steps, require expensive state-of-the-art lithographic equipment.
Further, even with such state-of-the-art lithographic equipment, overlay variations between two lithographic images are necessarily finite. With continual reduction in feature size and the limited capabilities of lithographic tools to scale overlay tolerance with the scaling of feature sizes of metal lines and metal vias, the overlay variations between the image of via cavities and line cavities may statistically result in a significant reduction in contact area between metal vias and metal lines and adversely affect yield, performance, and/or reliability of the metal interconnect structure.
In view of the above, there exists a need to provide a metal interconnect structure that may be manufactured with reduced processing cost through reduction in the number of lithographic steps employed to pattern via cavities and line cavities.
Further, there exists a need for a metal interconnect structure in which the overlay variation between a via cavity and a line cavity is reduced or eliminated so that yield, performance, and/or reliability of the metal interconnect structure is enhanced, and methods of manufacturing the same.